1. Field of the Invention
The present invention relates to a digital data converting method and apparatus therefor and, more particularly, to a digital data converting method and apparatus therefor suitable for use when a digital signal is transmitted or recorded.
2. Description of the Prior Art
An apparatus is known in which an analog signal, such as an audio signal or the like, is converted into a digital or PCM (pulse code modulated) audio signal, magnetically recorded in slant tracks on a magnetic tape by using a rotary head and without forming guardbands between the tracks, and then the audio signal is reproduced with high fidelity. In such known apparatus, during reproducing in addition to a differentiated output characteristic of the magnetic recording and a low frequency crosstalk component generated from adjacent tracks, a low frequency component of the reproduced signal is cut off by a rotary transformer used for transmitting signals to and from the rotary heads so that the low frequency component of the audio signal can not be reproduced with fidelity.
Accordingly, in the above apparatus which prefers a narrow record and playback frequency band and a small low frequency component, it is effective to modulate a record signal into the area of the low frequency component and DC component by a modulating system or format having a concentrated frequency spectrum. A modulation system or format generally called an NRZI (non-return to zero, inverted) is exemplified as one of such modulation systems. In the NRZI format, a binary "1" in the data signal, is represented by a transition of either positive or negative polarity, and a binary "0" is represented by the absence of a transition.
However, in the NRZI system, when consecutive digital zeroes appear, the modulated signal is not inverted, that is, there is no transition during that period and the frequency of the modulated signal becomes low with the result that the DC component or NRZI disparity and the low frequency component are increased.
Therefore, it is proposed to divide the PCM digital information into words comprised of a desired number of bits and to convert such information words into respective code words containing a larger number of bits and which are selected to avoid the occurrence of a large number of consecutive digital zeroes.
The present applicant has previously proposed such an information converting system as follows. This system employs a 8/10 converting scheme in which each eight bit word of digital information in a base digital is converted to a ten-bit word to form a converted digital signal. Eight bits (B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8) can be combined in 256 (2.sup.8) different ways, that is, can form 256 different 8-bit words. With ten bits, 1024 different 10-bits words or combinations are possible. Thus, 256 of the 1024 possible ten-bit combinations or words are used to represent respective eight-bit combinations or words.
In accordance with the conditions set forth above, there are certain constraints on which of the 256 ten-bit combinations or words can be used to represent respective eight-bit words. First, those conditions require that the DC component of the converted digital signal be zero. Second, because NRZI coding is being used, the number of consecutive digital zeroes in the converted digital signal must never exceed three, otherwise T.sub.max /T.sub.min (where T.sub.max is the maximum interval between level transitions and T.sub.min is minimum interval between transitions) will be greater than four.
The following table I shows the number of possible combinations of ten digital bits in NRZI code for which the DC component or disparity is zero, but in which there are not more than three digital zeroes in a row (either internally of each ten-bit word or at the juncture between two such words):
TABLE I ______________________________________ . . . 1 . . . 10 . . . 100 . . . 1000 ______________________________________ 1 . . . 69 34 14 4 01 . . . 40 20 8 1 001 . . . 20 10 3 1 0001 . . . 8 3 2 1 ______________________________________
Table I shows that there are numerous possible combinations that will satisfy the constraints. For example, if up to three digital zeroes are permitted at the beginning of each word, then no digital zeroes can be permitted at the end of any word, and in that case, Table I shows that the total of the possible combinations is: EQU 137=69+40+20+8
From all of the possible combinations in Table I, the maximum number of possible combinations having zero disparity is achieved if no more than two digital zeroes are permitted at the beginning of a ten-bit converted word and no more than one digital zero is permitted at the end. In that case, the total is: EQU 193=69+40 +20 +34+20+10
Thus, 193 ten-bit combinations are available for which the DC component or disparity is zero. These are hereinafter called "primary combinations."
Since there are 256 possible eight-bit words of original or base data, 63 additional ten-bit combinations or code words are required to represent all of the possible eight-bit words of original data. Thus, it is necessary to use ten-bit combinations for which the DC component or NRZI disparity is not zero.
The following table illustrates the number of possible ten-bit combinations, which begin with no more than two digital zeroes and end with no more than one digital zero, and for which the disparity or DC component is 0, -2 and +2 when NRZI-coded.
TABLE II ______________________________________ DC first bit -2 0 +2 ______________________________________ 1 . . . 11 . . . 52 40 103 60 100 43 101 11 30 30 100 1 13 27 01 . . . 43 60 40 001 . . . 30 30 11 ______________________________________
From Table II, it is clear that the number of possible combinations or ten-bit code words for which the DC component or disparity is -2 is expressed as EQU 52+43+30=125
Also it is made clear that the number of possible combinations with a DC component or disparity of +2 is expressed as EQU 100+40+11=151
To calculate the DC components or NRZI disparity for Table II, it was assumed that the exit polarity of the preceding code word or combination was negative or at low level, as shown in FIGS. 2A and 2B. If Table II were constructed by assuming that the exit polarity of the preceding code word was positive or high, then the "-2" and "+2" columns of Table II would be interchanged, as will be apparent from FIGS. 2A and 2B.
Further, the low frequency spectrum of the modulation wave tends to be decreased if code words or combinations with +2 and -2 DC components or disparities are used alternately more frequently than the code words or combinations with a zero DC component or disparity. Accordingly, 125 ten-bit combinations or code words paired to have +2 and -2 DC components or disparities, respectively, are used along with 131 combinations or code words with a zero DC component or disparity to represent the 256 combinations or information of 8 bits.
The paired combinations or code words with +2 and -2 DC components or disparities may be selected such that the DC component or disparity can be controlled only by changing or inverting the first bit of the respective code word. Therefore, of the possible combinations or code words on, for example, Table II, the combinations with +2 and -2 DC charges components or disparities and the first bit "0" number EQU 40+11+43+30=124
It is possible that those 124 combinations or code words and and a suitable number of the combinations or codes words with a zero DC charge, component or disparity in this case, 132 combinations are made corresponding to correspond one by one to 256 combinations or information words, of 8 bits. Then, each time a combination or code word with a .+-.2 DC component appears, the first bit of that code word is converted in such a manner that the DC components or disparities become positive and negative alternately.
For example as shown in FIGS. 3A and 3B, when a code word or combination with DC component or disparity of .+-.2 appears, the number of level transitions P (the number of digital "1") from the second bit is counted until the next combination or code word with .+-.2 DC component or disparity appears. Of the number of level transitions is even, the first bit (shown by an inverted delta or arrow) is converted to digital "1" as shown at the arrow in FIG. 3A, whereas if the number of level transitions is odd, the first bit of the next code word with .+-.2 disparity remains digital "0" as shown in FIG. 3B.
Thus, even if .+-.2 DC components appear, they are cancelled out by .+-.2 DC components of the succeeding combinations and hence regardless of any consecutive digital components, the overall DC component of the coded digital signal becomes zero.
By the way, the integral of the NRZI wave is generally called the DSV (digital sum variation) which is employed in one of the evaluation methods. Let it be considered that a code word or combination is formed of a 10-bit pattern. If the accumulation or summation of the disparities of the preceding code words has the value 1, that is, when the zero DC component or disparity as, for example, shown in FIG. 4A. When transition from the preceding code word begins with DSV=1, the DSV of the code word represented in FIG. 4A is that shown by a solid line in FIG. 4B.
If the width between the maximum and minimum values of the DSV is small, the DSV has small DC component block and the low frequency component is reduced. As one of the evaluation methods, it is known to use a parameter which is generally referred to as DSV variance. This DSV variance can be obtained by squaring and averaging DSV values of all bits and it is desired that this DSV variance be as small as possible. While the level of DSV=0 is defined as an average value of the DSV values all bits have, the DSV level for the waveform of the word which was NRZI-coded is defined as DSV max=-DSV min. Accordingly, in this case, it is convenient that the DSV at the boundary between the successive words is .+-.1 or -1 and the intermediate value between DSV max and DSV min is defined as DSV=0.
Therefore, let us consider the above converting method using the evaluation method of DSV variance. In the combination or code word as, for example, shown in FIG. 4A, when the evaluation of DSV variance begins with DSV=+1, the DSV changes along the solid line shown in FIG. 4B as described above and DSV variance at that time becomes 1.7. On the other hand when the evaluation of DSV variance begins with DSV=-1, the DSV changes as shown by a broken line in FIG. 4B and DSV variance at that time becomes 6.9. In other words, combinations or code words having the same bit pattern are made to have different DC characteristics depending on the initial setting of the DSV. Particularly, in this case when the evaluation of DSV variance begins with DSV=-1, the DSV variance becomes large, which is not desired.
FIG. 5 shows an example of an apparatus which is capable of eight-bit to ten-bit conversion in accordance with the above converting system. In FIG. 5, reference numeral 1 is an input terminal, 2 is an 8-bit shift register which accepts eight-bit information of 8 bits, 3 a conversion logic circuit which uses, for example, a programmable logic array (PLA), and 4 is a clock terminal. The information applied to the input terminal 1 is transferred 8 bits by 8 bits through the shift register 2 in response to a pulse which is applied to the clock terminal 4 at the data bit rate and the information words of 8 bits (B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8) are supplied to the conversion logic circuit 3.
Reference numeral 5 designates a data sync (synchronizing) pattern selecting circuit which is controlled for selection operation on the basis of a data/sync selection control signal applied to a terminal 6. When the movable contacts of this selecting circuit 5 are positioned to engage contacts a, a code word of 10 bits (P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, P.sub.6, P.sub.7, P.sub.8, P.sub.9, P.sub.10) which was generated in the above one-to-one conversion in the conversion logic circuit 3 is supplied to a 10-bit shift register 7. On the other hand, when the movable contacts of this selecting circuit 5 are changed in position to engage contacts b, the sync pattern which is always applied to contacts b is delivered from this selecting circuit 5. As this sync pattern, there is used a sync pattern of 10 bits which does not appear in this converting system, that is, does not correspond to any 10-bit code word.
Reference numeral 8 designates a detecting circuit which detects whether the first bit is made variable or fixed, namely that is, whether the combination has a zero DC component or a .+-.2 DC component. For example, this detecting circuit 8 may carry out modulo-addition for even-numbered bits of the outputs of the selecting circuit 5, or may detect whether the number of digital zeroes of the even-numbered bits is even or odd. When the detected number is zero (even), the detecting circuit 8 perceives therefrom that the combination has a .+-.2 DC component and, accordingly, detecting circuit 8 produces at its output a high level or digital "1". The output of detecting circuit 8 is supplied to one inut terminal of an AND circuit 9 and the AND circuit 9 is supplied at the other input terminal with an output from a detecting circuit 10 which is connected to the output of the shift register 7 for detecting DSV of each 10-bit code word or combination. This detecting circuit 10 supplies a high level or digital "1" output to the respective input of AND circuit 9 when the DSV at the exit of the preceding combination or code word is, for example, -1.
The output of the AND circuit 9 is supplied to one input terminal of an exclusive-OR (hereinafter simply referred to as EOR) circuit 11. To the other input terminal of this EOR circuit 11 is supplied a first bit P.sub.1 of the 10 bits from the selecting circuit 5. Accordingly, when the output of the AND circuit 9 is "0", the first bit P.sub.1 is not inverted in being fed to the shift register 7. However, when the output of the AND circuit 9 is "1", the first bit P.sub.1 is inverted in polarity in being fed through EOR 11 to the shift register 7.
As to the combination of a code word or combination with zero DC component or disparity and a code word or combination with .+-.2 DC component or disparity, the conversion logic circuit 3 is adapted to produce any one of such disparities. In this connection, when the conversion logic circuit 3 produces a converted code word or combination which has -2 DC component or disparity and the evaluation of DSV variance begins with -1, that is, DSV=-1 at the exit of the preceding code word, the first bit of the code word from circuit 3 is inverted in level by the EOR circuit 11 (at this time, the output of the AND circuit 9 is at a high level) and then is produced a code word or combination having +2 DC component or disparity. Since the output of the detecting circuit 8 is at a low level and the output of the AND circuit 9 is at a low level for a code word or combination with a zero DC component, such code word is directly transmitted to register 7 without its first bit being inverted in level by the EOR circuit 11.
Further, a timing detecting circuit 12 detects the timing of the pulse which is applied to the clock terminal 1 at the data bit rate and the timing signal from the timing detecting circuit 12 is supplied to a load terminal LD of the shift register 7 at every 8 bits of data.
As described above, the content or data converted to the form of 10 bit data and latched in the shift register 7 is sequentially read out therefrom on the basis of a clock signal with a frequency 5/4 times the clock frequency of the input signal and supplied to shift register 7 from a clock terminal 13. The signal thus read out is supplied to, for example, a T-type flip-flop circuit 14 serving as an NRZI-coding circuit, and on the basis of the clock signal applied from the clock terminal 13 to the clock terminal of this flip-flop circuit 14, the flip-flop circuit 14 produces an NRZI coded signal at an output terminal 15.
FIG. 6 schematically shows an example of an apparatus for demodulating the information which was modulated by the apparatus of FIG. 5 in accordance with the above described method.
In FIG. 6, reference numeral 21 designates an input terminal to which a signal is supplied through an NRZI demodulating circuit 22, whereupon, the resulting 10-bit demodulated code word is applied to a 10-bit shift register 23. The code word of ten bits is transferred throughout the 10-bit shift register 23 on the basis at a pulse of the code bit rate supplied thereto from a clock terminal 24. Each code word of ten bits, P.sub.1 to P.sub.10 from the shift register 23 is supplied to a conversion logic circuit 25 which uses, for example, a PLA (programmable logic array).
Also connected to the output of the demodulating circuit 22 is a detecting circuit 26 which detects the DSV of each code word or combination, and the output of this detecting circuit 26 is supplied to one input terminal of an EOR circuit 27. To the other input terminal of the EOR circuit 27 is supplied the first bit P.sub.1 of the output from the shift register 23. In this case, the input to the conversion logic circuit 25 is either a code word or combination with a zero DC component or disparity or a code word or combination which .+-.2 DC component or disparity. The detecting circuit 26 produces a high level or logic "1" output when the DSV at the exit of the preceding code word or combination is =1. Accordingly, when supplied with a combination with a +2 DC component or disparity from the shift register 23, the EOR circuit 27 inverts its first bit P.sub.1 and passes the same to circuit 25, while when supplied with a combination with a -2 DC component from the shift register 23, the EOR circuit 27 passes on the first bit as it is.
In the conversion logic circuit 25, the code word of ten bits, P.sub.1 to P.sub.10 is demodulated using one-to-one reverse conversion. Accordingly, the demodulated information word of eight bits, B.sub.1 to B.sub.8 is delivered to an 8-bit shift register 28 and then latched therein each time a timing signal (a pulse of each block), which results from detecting by a timing detecting circuit 30, and is applied to a load terminal LD of the shift register 28. Then, the content or data of the shift register 28 is shifted bit by bit on the basis of the pulse which is applied from a terminal 29 to its clock terminal at a data bit rate thereby to provide the information data at an output terminal 31.
As described above, the modulation and demodulation of information can be carried out.
By the way, in the case of the circuit arrangement in which a PLA is used for the conversion logic circuit 3 or 25 as described above, a circuit for detecting whether the combination has a zero DC component or .+-.2 DC components or the like is required so that the circuit arrangement becomes complicated. This poses no problem when a ROM (read-only memory) is used as the conversion logic circuit 3 or 25. However, the use of a ROM causes the circuit arrangement to become large, and when this ROM is formed as an IC (integrated circuit), the ROM occupies a large area and consumes much power.
Further, if the paired combinations or code words are not limited to code words in which bits from the second bits on are equal but are selected from code words having small DSV variance, although the DSV variance can be made smaller, it is unavoidable that the circuit arrangement becomes even more complex.
Furthermore, an 8-bit to 9-bit conversion NRZI-coding system is disclosed in the Published British Patent Application No. 2101854 the applicant of which is same as the assignee of this application. In such NRZI-coding system, the maximum interval (T max) between level transitions exceeds 14 bit cells, the DC components or disparities of modulated words are as large as +4 or -9 and further DSV variance is large.